After ICs are fabricated on a wafer, a wafer sawing process is followed to saw a clean wafer into a plurality of square dies so-called singulation. During the wafer sawing process, a dicing blade saws along the scribe lines on a clean wafer. However, in advanced wafer level packaging process, a dielectric layer is coated on a wafer to pre-packaging IC chips, to avoid moisture penetration and particles attachment, to serve as an adhesive for chip bonding, to create electrical isolation, or to serve as an encapsulating material for protecting bumps. Since the scribe lines are covered by the dielectric layer, therefore, accurate alignment for wafer sawing process becomes difficult.
In U.S. Pat. No. 6,455,353 B2, Lin discloses a dam disposed at the peripheries of a wafer so that encapsulant is completely filled in the enclosed area by the dam. Then, by removing the dam or by designing a dam smaller than a wafer, parts of the scribe lines at the peripheries of a wafer are exposed as the alignment points for wafer sawing process. However, the exposed portions of the scribe lines located at the peripheries of a wafer are incomplete and fickle due to encapsulation process, therefore, it is not easy to decide which points are the alignment points leading to misalignment. Moreover, the exposed patterns of the scribe lines are greatly affected by the dimension variation of a dam where the pattern recognition by the image processing system of the sawing equipment become difficult leading to sawing through chips instead of along the scribe lines. Furthermore, since the dam occupy certain footprint of the wafer where the wafer area covered by the dam will become bad dies or unpackaged bare dies leading to decrease of effective die area of a wafer with complicated process issues. Moreover, encapsulant is disposed on a wafer in a liquid form with poor coplanarity on the surface where more lapping time for planarization is required in the following processing steps leading to higher risks of the contaminations.